Divider value when the Uart clock source is selected as FCLK/n.
’n’ is determined by UCON0[15:12], UCON1[15:12], UCON2[14:12].
UCON2[15] is FCLK/n Clock Enable/Disable bit.
For setting ‘n’ from 7 to 21, use UCON0[15:12],
For setting ‘n’ from 22 to 36, use UCON1[15:12],
For setting ‘n’ from 37 to 43, use UCON2[14:12],
UCON2[15]: 0 = Disable FCLK/n clock. 1 = Enable FCLK/n clock.
In case of UCON0,
UART clock = FCLK / (divider+6), where divider>0.
!!!(1)UCON1, UCON2 must be zero.
ex) 1: UART clock = FCLK/7, 2: UART clock = FCLK/8
3: UART clock = FCLK/9, … , 15: UART clock = FCLK/21
In case of UCON1,
UART clock = FCLK / (divider+21), where divider>0.
!!!(2)UCON0, UCON2 must be zero.
ex) 1: UART clock = FCLK/22, 2: UART clock = FCLK/23
3: UART clock = FCLK/24, … , 15: UART clock = FCLK/36
In case of UCON2,
UART clock = FCLK / (divider+36), where divider>0.
UCON0, UCON1 must be zero.
ex) 1: UART clock = FCLK/37, 2: UART clock = FCLK/38
3: UART clock = FCLK/39, … , 7: UART clock = FCLK/43
!!!(3)If UCON00/1[15:12] and UCON2[14:12] are all ‘0’, the divider will be
!!!(3)44, that is UART clock =FCLK/44
!!!(3)Total division range is from 7 to 44.
想问一下 (1)第一处的问题 UCON1, UCON2 must be zero. ? 到底是 UCON1[12--15] UCON2[12--14] 为0 吗?
(3) 1. UCON00/1[15:12] ??? 是要表示 UCON0[15:12]的意思吗? 2. 是不是只要满足 If UCON00/1[15:12] and UCON2[14:12] are all ‘0’ 的时候不管 其它不管怎么设置都是 FCLK/44
(4): 在裸奔3的代码中init_uart 中 , UCON 0/1/2 =0x245 那么UART 的使能 UCON2[15]=0 莫非URAT无源可以工作? |