NK->Startup.s里面的内容:
; Clear RAM.
;
; mov r1,#0
; mov r2,#0
; mov r3,#0
; mov r4,#0
; mov r5,#0
; mov r6,#0
; mov r7,#0
; mov r8,#0
; ldr r0,=0x30000000 ; Start address (physical 0x3000.0000).
; ldr r9,=0x04000000 ; 64MB of RAM.
;20
; stmia r0!, {r1-r8}
; subs r9, r9, #32
; bne %B20
; The page tables and exception vectors are setup.
; Initialize the MMU and turn it on.
mov r1, #1
mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r10, c2, c0, 0
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
; mov r1, #0x0071 ; Enable: MMU
mrc p15, 0, r1, c1, c0, 0
and r1, r1, #0xC0000000 ; [31:30] AsyncBusMode Enable, [12] ICache Disable(UMON set enable)
orr r1, r1, #0x0079 ; [0] Enable MMU, [6:3] Reserved 1111
orr r1, r1, #0x4000 ; Round-Robind Cache Replacement Policy
orr r1, r1, #0x1000 ; Enable ICache (with MMU On)
orr r1, r1, #0x0004 ; Enable the cache
; Initialize stacks.
;
30
mrs r0, cpsr
bic r0, r0, #MODEMASK|NOINT
orr r1, r0, #SVCMODE
msr cpsr_cxsf, r1 ; SVCMode.
ldr sp, =SVCStack
; Jump to main C routine.
;
bl main
40
ldr r4, =0x200000
add r4, r4, #0x30000000
mov pc, r4
b .
; b led_loop
led_loop
ldr r0, =GPBCON
ldr r1, =0x15400
str r1, [r0]
ldr r0, =GPBDAT
ldr r1, =0x1E0
str r1, [r0]
ldr r0, =0x100000
100 subs r0, r0, #1
bne %B100
ldr r0, =GPBDAT
ldr r1, =0x00
str r1, [r0]
ldr r0, =0x100000
200 subs r0, r0, #1
bne %B200
b led_loop
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance .
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz.
;
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;100MHz
DCD 0x32 ; SCLK power saving mode, BANKSIZE 128M/128M, 4-burst.
DCD 0x30 ; MRSR6 CL=3clk.
DCD 0x30 ; MRSR7.
;------------------------------------
; MMU Cache/TLB/etc on/off functions
;------------------------------------
R1_I EQU (1<<12)
R1_C EQU (1<<2)
R1_A EQU (1<<1)
R1_M EQU (1)
R1_iA EQU (1<<31)
R1_nF EQU (1<<30)
; void MMU_EnableICache(void);
;
LEAF_ENTRY MMU_EnableICache
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_I
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; void MMU_SetAsyncBusMode(void);
; FCLK:HCLK= 1:2
;
LEAF_ENTRY MMU_SetAsyncBusMode
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; NAND code...
;
A410_BASE_ADDR EQU 0x2000000
;;; MACRO
;;; LDR4STR1 $src,$tmp1,$tmp2
;;; ldrb $tmp1,[$src]
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #8
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #16
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #24
;;; MEND
EXPORT __RdPagedata
__RdPagedata
;input:a1(r0)=pPage
stmfd sp!,{r1-r11}
ldr r1,=0x4e000010 ;NFDATA
mov r2,#0x200
10
ldr r4,[r1]
ldr r5,[r1]
ldr r6,[r1]
ldr r7,[r1]
ldr r8,[r1]
ldr r9,[r1]
ldr r10,[r1]
ldr r11,[r1]
stmia r0!,{r4-r11}
subs r2,r2,#32
bne %B10
ldmfd sp!,{r1-r11}
mov pc,lr
END
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