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天嵌TQ210v4开发板+7寸电容屏+包邮=719元!samsung cortex-a8
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[已解决] am335x的网卡相关资料

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freewing 发表于 2015-8-18 16:50:38 | 显示全部楼层 |阅读模式
其他网站看到的am335x的网卡移植参考程序,供大家参考。
  1. http://www.deyisupport.com/question_answer/dsp_arm/sitara_arm/f/25/t/46117.aspx
  2. /*
  3. * Code for AM335X EVM.
  4. *
  5. * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY ofany
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/i2c.h>
  19. #include <linux/module.h>
  20. #include <linux/i2c/at24.h>
  21. #include <linux/phy.h>
  22. #include <linux/gpio.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/flash.h>
  25. #include <linux/gpio_keys.h>
  26. #include <linux/input.h>
  27. #include <linux/input/matrix_keypad.h>
  28. #include <linux/mtd/mtd.h>
  29. #include <linux/mtd/nand.h>
  30. #include <linux/mtd/partitions.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/clk.h>
  33. #include <linux/err.h>
  34. #include <linux/export.h>
  35. #include <linux/wl12xx.h>
  36. #include <linux/ethtool.h>
  37. #include <linux/mfd/tps65910.h>
  38. #include <linux/mfd/tps65217.h>
  39. #include <linux/pwm_backlight.h>
  40. #include <linux/input/ti_tsc.h>
  41. #include <linux/platform_data/ti_adc.h>
  42. #include <linux/mfd/ti_tscadc.h>
  43. #include <linux/reboot.h>
  44. #include <linux/pwm/pwm.h>
  45. #include <linux/rtc/rtc-omap.h>
  46. #include <linux/opp.h>
  47. /* LCDcontroller is similar to DA850 */
  48. #include <video/da8xx-fb.h>
  49. #include<mach/hardware.h>
  50. #include <mach/board-am335xevm.h>
  51. #include<asm/mach-types.h>
  52. #include <asm/mach/arch.h>
  53. #include <asm/mach/map.h>
  54. #include <asm/hardware/asp.h>
  55. #include<plat/omap_device.h>
  56. #include <plat/omap-pm.h>
  57. #include <plat/irqs.h>
  58. #include <plat/board.h>
  59. #include <plat/common.h>
  60. #include <plat/lcdc.h>
  61. #include <plat/usb.h>
  62. #include <plat/mmc.h>
  63. #include <plat/emif.h>
  64. #include <plat/nand.h>
  65. #include"board-flash.h"
  66. #include "cpuidle33xx.h"
  67. #include "mux.h"
  68. #include "devices.h"
  69. #include "hsmmc.h"
  70. /* ConvertGPIO signal to GPIO pin number */
  71. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  72. /* BBB PHYIDs */
  73. #define BBB_PHY_ID  0x7c0f1
  74. #define BBB_PHY_MASK  0xfffffffe
  75. /* AM335X EVMPhy ID and Debug Registers */
  76. #define AM335X_EVM_PHY_ID  0x4dd074
  77. #define AM335X_EVM_PHY_MASK  0xfffffffe
  78. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  79. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  80. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  81. #define AR8051_RGMII_TX_CLK_DLY  BIT(8)
  82. /*
  83. #define CONFIG_DH_320_240         1
  84. #define CONFIG_DH_480_272         2
  85. #define CONFIG_DH_800_480         3
  86. #define CONFIG_DH_800_600         4*/
  87. static const struct display_panel disp_panel = {
  88. WVGA,
  89. 32,
  90. 16,//32, --czx
  91. COLOR_ACTIVE,
  92. };
  93. /* LCDbacklight platform Data */
  94. #defineAM335X_BACKLIGHT_MAX_BRIGHTNESS        100
  95. #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
  96. #defineAM335X_PWM_PERIOD_NANO_SECONDS        (5000* 10)
  97. static structplatform_pwm_backlight_data am335x_backlight_data0 = {
  98. .pwm_id         ="ecap.0",
  99. .ch            = -1,
  100. .lth_brightness = 21,
  101. .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
  102. .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
  103. .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
  104. };
  105. static structplatform_pwm_backlight_data am335x_backlight_data2 = {
  106. .pwm_id         ="ecap.2",
  107. .ch            = -1,
  108. .lth_brightness = 21,
  109. .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
  110. .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
  111. .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
  112. };
  113. static structlcd_ctrl_config lcd_cfg = {
  114. //#if defined(CONFIG_DH_320_240)||(CONFIG_DH_480_272)||(CONFIG_DH_800_480)||(CONFIG_DH_800_600)
  115. /*&disp_panel,
  116. .ac_bias  = 255,
  117. .ac_bias_intrpt  = 0,
  118. .dma_burst_sz  = 16,
  119. .bpp   = 16,//32,--czx
  120. .fdd   = 0x80,
  121. .tft_alt_mode  = 0,
  122. .stn_565_mode  = 0,
  123. .mono_8bit_mode  = 0,
  124. .invert_line_clock = 1,
  125. .invert_frm_clock = 1,
  126. .sync_edge  = 0,
  127. .sync_ctrl  = 1,
  128. .raster_order  = 0,*/
  129. //#elif defined CONFIG_VGA
  130.         &disp_panel,
  131. .ac_bias  = 255,
  132. .ac_bias_intrpt  = 0,
  133. .dma_burst_sz  = 16,
  134. .bpp   = 16,//32,--czx
  135. .fdd   = 0x80,
  136. .tft_alt_mode  = 0,
  137. .stn_565_mode  = 0,
  138. .mono_8bit_mode  = 0,
  139. .invert_line_clock = 1,
  140. .invert_frm_clock = 1,
  141. .sync_edge  = 0,
  142. .sync_ctrl  = 1,
  143. .raster_order  = 0,
  144. //#endif
  145. };
  146. structda8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
  147. .manu_name  = "ThreeFive",
  148. .controller_data = &lcd_cfg,
  149. .type   = "TFC_S9700RTWV35TR_01B",
  150. };
  151. structda8xx_lcdc_platform_data  NHD_480272MF_ATXI_pdata = {
  152. .manu_name             = "NHD",
  153. .controller_data        =&lcd_cfg,
  154. .type                  = "NHD-4.3-ATXI#-T-1",
  155. };
  156. // --czx
  157. structda8xx_lcdc_platform_data  YL_LCD_pdata = {
  158. .manu_name             = "DH",
  159. .controller_data        =&lcd_cfg,
  160. #if defined (CONFIG_DH_320_240)
  161. .type                  = "YL_LCD35",
  162. #elif defined(CONFIG_DH_480_272)
  163. .type                  = "YL_LCD43",
  164. #elif defined(CONFIG_DH_800_480)
  165. .type                  = "YL_LCD70",
  166. #elif definedCONFIG_DH_800_600
  167. .type                  = "YL_LCD80",
  168. #elif definedCONFIG_VGA
  169. .type                  = "YL_VGA",
  170. #endif
  171. };

  172. //end
  173. #include "common.h"

  174. /* TSc controller */
  175. static structtsc_data am335x_touchscreen_data  = {
  176. .wires  = 4,
  177. .x_plate_resistance = 200,
  178. .steps_to_configure = 5,
  179. };

  180. static struct adc_data am335x_adc_data = {
  181. .adc_channels = 4,
  182. };
  183. static structmfd_tscadc_board tscadc = {
  184. .tsc_init = &am335x_touchscreen_data,
  185. .adc_init = &am335x_adc_data,
  186. };
  187. static u8am335x_evm_sk_iis_serializer_direction1[] = {
  188. RX_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
  189. INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
  190. INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
  191. INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
  192. };

  193. static struct snd_platform_data am335x_evm_snd_data1 = {
  194. .tx_dma_offset = 0x46400000, /* McASP1 */
  195. .rx_dma_offset = 0x46400000,
  196. .op_mode = DAVINCI_MCASP_IIS_MODE,
  197. .num_serializer =ARRAY_SIZE(am335x_evm_sk_iis_serializer_direction1),
  198. .tdm_slots = 2,
  199. .serial_dir = am335x_evm_sk_iis_serializer_direction1,
  200. .asp_chan_q = EVENTQ_2,
  201. .version = MCASP_VERSION_3,
  202. .txnumevt = 1,
  203. .rxnumevt = 1,
  204. .get_context_loss_count =
  205.    omap_pm_get_dev_context_loss_count,
  206. };
  207. static structsnd_platform_data am335x_evm_sk_snd_data1 = {
  208. .tx_dma_offset = 0x46400000, /* McASP1 */
  209. .rx_dma_offset = 0x46400000,
  210. .op_mode = DAVINCI_MCASP_IIS_MODE,
  211. .num_serializer =ARRAY_SIZE(am335x_evm_sk_iis_serializer_direction1),
  212. .tdm_slots = 2,
  213. .serial_dir = am335x_evm_sk_iis_serializer_direction1,
  214. .asp_chan_q = EVENTQ_2,
  215. .version = MCASP_VERSION_3,
  216. .txnumevt = 1,
  217. .rxnumevt = 1,
  218.   .get_context_loss_count =
  219.       omap_pm_get_dev_context_loss_count,
  220. };
  221. static structomap2_hsmmc_info am335x_mmc[] __initdata = {
  222. {
  223.   .mmc           = 1,
  224.   .caps           =MMC_CAP_4_BIT_DATA,
  225.   .gpio_cd        = GPIO_TO_PIN(0,6),
  226.   .gpio_wp        =-EINVAL,//GPIO_TO_PIN(3, 18),//--czx
  227.   .ocr_mask       = MMC_VDD_32_33 |MMC_VDD_33_34, /* 3V3 */
  228. },
  229. {
  230.   .mmc           = 0, /* will be set at runtime */
  231. },
  232. {
  233.   .mmc           = 0, /* will be set at runtime */
  234. },
  235. {}      /* Terminator */
  236. };
  237. #ifdefCONFIG_OMAP_MUX
  238. static structomap_board_mux board_mux[] __initdata = {
  239. /*
  240.   * Setting SYSBOOT[5] should set xdma_event_intr0 pin to mode 3 thereby
  241.   * allowing clkout1 to be available on xdma_event_intr0.
  242.   * However, on some boards (like EVM-SK), SYSBOOT[5] isn't properly
  243.   * latched.
  244.   * To be extra cautious, setup the pin-mux manually.
  245.   * If any modules/usecase requries it in different mode, then subsequent
  246.   * module init call will change the mux accordingly.
  247.   */
  248. AM33XX_MUX(XDMA_EVENT_INTR0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT),
  249. AM33XX_MUX(I2C0_SDA,OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
  250.                        AM33XX_INPUT_EN |AM33XX_PIN_OUTPUT),
  251. AM33XX_MUX(I2C0_SCL,OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
  252.    AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
  253. {.reg_offset = OMAP_MUX_TERMINATOR },
  254. };
  255. #else
  256. #define board_mux NULL
  257. #endif
  258. /* module pinmux structure */
  259. struct pinmux_config {
  260. const char *string_name; /* signal name format */
  261. int val; /* Options for the mux register value */
  262. };
  263. structevm_dev_cfg {
  264. void (*device_init)(int evm_id, int profile);
  265. /*
  266. * If the device is required on both baseboard & daughter board (ex i2c),
  267. * specify DEV_ON_BASEBOARD
  268. */
  269. #define DEV_ON_BASEBOARD 0
  270. #define DEV_ON_DGHTR_BRD 1
  271. u32 device_on;
  272. u32profile; /* Profiles (0-7) in which the module is present */
  273. };
  274. /* AM335X -CPLD Register Offsets */
  275. #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
  276. #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
  277. #define CPLD_DEVICE_REV 0x0C/* Revision of the CPLD code */
  278. #define CPLD_CFG_REG 0x10 /* Configuration Register */
  279. static structi2c_client *cpld_client;
  280. static u32 am335x_evm_id;
  281. static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
  282. };
  283. /*
  284. * EVM Config held in On-Board eeprom device.
  285. *
  286. * Header Format
  287. *
  288. *  Name   Size Contents
  289. *   (Bytes)
  290. *-------------------------------------------------------------
  291. *  Header  4 0xAA, 0x55, 0x33, 0xEE
  292. *
  293. *  Board Name  8 Name for board in ASCII.
  294. *    Example "A33515BB" = "AM335x 15x15 BaseBoard"
  295. *
  296. *  Version  4 Hardware version code for board inASCII.
  297. *    "1.0A"= rev.01.0A
  298. *
  299. *  Serial Number 12 Serial number of the board. This is a 12
  300. *    character string which is WWYY4P16nnnn, where
  301. *    WW = 2 digit week of the year of production
  302. *    YY = 2 digit year of production
  303. *    nnnn = incrementing board number
  304. *
  305. *  Configuration option 32 Codes(TBD) to show the configuration
  306. *    setup on this board.
  307. *
  308. *  Available  32720 Available space for other non-volatiledata.
  309. */
  310. struct am335x_evm_eeprom_config {
  311. u32 header;
  312. u8 name[8];
  313. char version[4];
  314. u8 serial[12];
  315. u8 opt[32];
  316. };
  317. /*
  318. * EVM Config held in daughter board eeprom device.
  319. *
  320. * Header Format
  321. *
  322. *  Name   Size  Contents
  323. *   (Bytes)
  324. *-------------------------------------------------------------
  325. *  Header  4 0xAA, 0x55, 0x33, 0xEE
  326. *
  327. *  Board Name  8 Name for board in ASCII.
  328. *    example "A335GPBD" = "AM335x
  329. *    General Purpose Daughterboard"
  330. *
  331. *  Version  4 Hardware version code for board in
  332. *    in ASCII. "1.0A" = rev.01.0A
  333. *  Serial Number 12 Serial number of the board. This is a 12
  334. *    character string which is: WWYY4P13nnnn, where
  335. *    WW = 2 digit week of the year of production
  336. *    YY = 2 digit year of production
  337. *    nnnn = incrementing board number
  338. *  Configuration Option 32 Codes to show the configuration
  339. *    setup on this board.
  340. *  CPLD Version 8  CPLD code version for board in ASCII
  341. *    "CPLD1.0A"= rev. 01.0A of theCPLD
  342. *  Available 32700  Available space for other non-volatile
  343. *    codes/data
  344. */
  345. structam335x_eeprom_config1 {
  346. u32 header;
  347. u8 name[8];
  348. char version[4];
  349. u8 serial[12];
  350. u8 opt[32];
  351. u8 cpld_ver[8];
  352. };
  353. static structam335x_evm_eeprom_config config;
  354. static struct am335x_eeprom_config1 config1;
  355. static bool daughter_brd_detected;
  356. #defineEEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
  357. #define EEPROM_NO_OF_MAC_ADDR  3
  358. static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
  359. #defineAM335X_EEPROM_HEADER  0xEE3355AA
  360. static intam33xx_evmid = -EINVAL;
  361. /*
  362. * am335x_evm_set_id - set up board evmid
  363. * @evmid - evm id which needs to be configured
  364. *
  365. * This function is called to configure board evm id.
  366. */
  367. void am335x_evm_set_id(unsigned int evmid)
  368. {
  369. am33xx_evmid = evmid;
  370. return;
  371. }
  372. /*
  373. * am335x_evm_get_id - returns Board Type (EVM/BB/EVM-SK ...)
  374. *
  375. * Note:
  376. * returns -EINVAL if Board detection hasn't happened yet.
  377. */
  378. int am335x_evm_get_id(void)
  379. {
  380. return am33xx_evmid;
  381. }
  382. EXPORT_SYMBOL(am335x_evm_get_id);
  383. /* currentprofile if exists else PROFILE_0 on error */
  384. static u32 am335x_get_profile_selection(void)
  385. {
  386. int val = 0;
  387. if(!cpld_client)
  388.   /* error checking is not done in func's calling this routine.
  389.   so return profile 0 on error */
  390.   return 0;
  391. val = i2c_smbus_read_word_data(cpld_client,CPLD_CFG_REG);
  392. if (val < 0)
  393.   return 0; /* default to Profile 0 on Error */
  394. else
  395.   return val & 0x7;
  396. }
  397. static structpinmux_config haptics_pin_mux[] = {
  398. {"gpmc_ad9.ehrpwm2B",  OMAP_MUX_MODE4 |
  399.   AM33XX_PIN_OUTPUT},
  400. {NULL, 0},
  401. };
  402. /* Module pinmux for LCDC */
  403. static struct pinmux_config lcdc_pin_mux[] = {
  404. {"lcd_data0.lcd_data0",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  405.              |AM33XX_PULL_DISA},
  406. {"lcd_data1.lcd_data1",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  407.              |AM33XX_PULL_DISA},
  408. {"lcd_data2.lcd_data2",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  409.              |AM33XX_PULL_DISA},
  410. {"lcd_data3.lcd_data3",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  411.              |AM33XX_PULL_DISA},
  412. {"lcd_data4.lcd_data4",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  413.              |AM33XX_PULL_DISA},
  414. {"lcd_data5.lcd_data5",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  415.              | AM33XX_PULL_DISA},
  416. {"lcd_data6.lcd_data6",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  417.              |AM33XX_PULL_DISA},
  418. {"lcd_data7.lcd_data7",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  419.              |AM33XX_PULL_DISA},
  420. {"lcd_data8.lcd_data8",  OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
  421.              |AM33XX_PULL_DISA},
  422. {"lcd_data9.lcd_data9",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  423.              |AM33XX_PULL_DISA},
  424. {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  425.              |AM33XX_PULL_DISA},
  426. {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  427.              |AM33XX_PULL_DISA},
  428. {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  429.              |AM33XX_PULL_DISA},
  430. {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  431.              | AM33XX_PULL_DISA},
  432. {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  433.              |AM33XX_PULL_DISA},
  434. {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT
  435.              |AM33XX_PULL_DISA},
  436. {"lcd_vsync.lcd_vsync",  OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
  437. {"lcd_hsync.lcd_hsync",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT},
  438. {"lcd_pclk.lcd_pclk",  OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT},
  439. {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT},
  440. {NULL, 0},
  441. };
  442. static structpinmux_config tsc_pin_mux[] = {
  443. {"ain0.ain0",          OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  444. {"ain1.ain1",          OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  445. {"ain2.ain2",          OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  446. {"ain3.ain3",          OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  447. {"vrefp.vrefp",        OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  448. {"vrefn.vrefn",        OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
  449. {NULL, 0},
  450. };
  451. /* Pin muxfor nand flash module */
  452. static struct pinmux_config nand_pin_mux[] = {
  453. {"gpmc_ad0.gpmc_ad0",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  454. {"gpmc_ad1.gpmc_ad1",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  455. {"gpmc_ad2.gpmc_ad2",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  456. {"gpmc_ad3.gpmc_ad3",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  457. {"gpmc_ad4.gpmc_ad4",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  458. {"gpmc_ad5.gpmc_ad5",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  459. {"gpmc_ad6.gpmc_ad6",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  460. {"gpmc_ad7.gpmc_ad7",   OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  461. {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  462. {"gpmc_wpn.gpmc_wpn",   OMAP_MUX_MODE7 |AM33XX_PIN_INPUT_PULLUP},
  463. {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 |AM33XX_PULL_DISA},
  464. {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 |AM33XX_PULL_DISA},
  465. {"gpmc_oen_ren.gpmc_oen_ren",  OMAP_MUX_MODE0 |AM33XX_PULL_DISA},
  466. {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 |AM33XX_PULL_DISA},
  467. {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 |AM33XX_PULL_DISA},
  468. {NULL, 0},
  469. };
  470. /* Module pinmux for rgmii1 */
  471. static struct pinmux_config rgmii1_pin_mux[] = {
  472. {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  473. {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  474. {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  475. {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  476. {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  477. {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  478. {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  479. {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  480. {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  481. {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  482. {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
  483. {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  484. {"mdio_data.mdio_data", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  485. {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT_PULLUP},
  486. {NULL, 0},
  487. };
  488. /* Module pinmux for rgmii2 */
  489. static struct pinmux_config rgmii2_pin_mux[] = {
  490. {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  491. {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  492. {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  493. {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  494. {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  495. {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  496. {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
  497. {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  498. {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  499. {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  500. {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
  501. {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLDOWN},
  502. {"mdio_data.mdio_data", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  503. {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT_PULLUP},
  504. {NULL, 0},
  505. };
  506. static structpinmux_config i2c0_pin_mux[]= {
  507.         {"i2c0_sda.i2c0_sda",   OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
  508.                                        AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
  509.         {"i2c0_scl.i2c0_scl",  OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
  510.                                        AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
  511.         {NULL, 0},
  512. };

  513. /* Module pin mux for mcasp1 */
  514. static struct pinmux_config mcasp1_pin_mux[] = {
  515. {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 |AM33XX_PIN_INPUT_PULLDOWN},
  516. {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 |AM33XX_PIN_INPUT_PULLDOWN},
  517. {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 |AM33XX_PIN_INPUT_PULLDOWN},
  518. {"rmii1_refclk.mcasp1_ahclkx", OMAP_MUX_MODE6|AM33XX_PIN_OUTPUT},
  519. {"mcasp0_ahclkx.mcasp1_axr1", OMAP_MUX_MODE3 |AM33XX_PIN_INPUT_PULLDOWN},
  520. {NULL, 0},
  521. };

  522. /* Module pin mux for mmc0 */
  523. static struct pinmux_config mmc0_common_pin_mux[] = {
  524. {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  525. {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  526. {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  527. {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  528. {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  529. {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
  530. {NULL, 0},
  531. };

  532. static struct pinmux_config uart4_pin_mux[] ={                              
  533. {"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
  534. {"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PULL_ENBL},
  535. {NULL, 0},
  536. };
  537. static structpinmux_config d_can_gp_pin_mux[] = {
  538. {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
  539. {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 |AM33XX_PIN_INPUT_PULLUP},
  540. {NULL, 0},
  541. };
  542. /* pinmux forgpio based key */
  543. static struct pinmux_config gpio_keys_pin_mux[] ={                     //lh
  544. {"mcasp0_aclkx.gpio3_14", OMAP_MUX_MODE7 |AM33XX_PIN_INPUT},//K1
  545. {"mcasp0_fsx.gpio3_15", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
  546. {"mcasp0_axr0.gpio3_16", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
  547. {"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
  548. {NULL, 0},
  549. };
  550. /* pinmux forled device */
  551. static struct pinmux_config gpio_led_mux[] ={                     //lh
  552. {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 |AM33XX_PIN_OUTPUT},
  553. {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
  554. {NULL, 0},
  555. };

  556. /*
  557. * @pin_mux - single module pin-mux structure which defines pin-mux
  558. *   details for all its pins.
  559. */
  560. static void setup_pin_mux(struct pinmux_config *pin_mux)
  561. {
  562. int i;
  563. for (i= 0; pin_mux->string_name != NULL; pin_mux++)
  564.   omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
  565. }
  566. static structgpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
  567. /*.buttons        =am335x_evm_volume_gpio_buttons,
  568. .nbuttons       =ARRAY_SIZE(am335x_evm_volume_gpio_buttons),*/
  569. };
  570. static structplatform_device am335x_evm_volume_keys = {
  571. .name   = "gpio-keys",
  572. .id     = -1,
  573. .dev    = {
  574.   .platform_data  = &am335x_evm_volume_gpio_key_info,
  575. },
  576. };
  577. static voidvolume_keys_init(int evm_id, int profile)
  578. {
  579. int err;
  580. //setup_pin_mux(volume_keys_pin_mux);
  581. err = platform_device_register(&am335x_evm_volume_keys);
  582. if (err)
  583.   pr_err("failed to register matrix keypad (2x3)device\n");
  584. }
  585. /*
  586. * @evm_id - evm id which needs to be configured
  587. * @dev_cfg - single evm structure which includes
  588. *    all module inits, pin-mux defines
  589. * @profile - if present, else PROFILE_NONE
  590. * @dghtr_brd_flg - Whether Daughter board is present or not
  591. */
  592. static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
  593. int profile)
  594. {
  595. int i;
  596. am335x_evm_set_id(evm_id);
  597. /*
  598. * Only General Purpose & Industrial Auto Motro Control
  599. * EVM has profiles. So check if this evm has profile.
  600. * If not, ignore the profile comparison
  601. */
  602. /*
  603. * If the device is on baseboard, directly configure it. Else (device on
  604. * Daughter board), check if the daughter card is detected.
  605. */
  606. if (profile == PROFILE_NONE) {
  607.   for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
  608.    pr_info("_configure_device %d \n",i);
  609.    if (dev_cfg->device_on == DEV_ON_BASEBOARD)
  610.     dev_cfg->device_init(evm_id, profile);
  611.    else if (daughter_brd_detected == true)
  612.     dev_cfg->device_init(evm_id, profile);
  613.   }
  614. } else {
  615.   for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
  616.    pr_info("_configure_device %d \n",i);
  617.    if (dev_cfg->profile & profile) {
  618.     if (dev_cfg->device_on == DEV_ON_BASEBOARD)
  619.      dev_cfg->device_init(evm_id, profile);
  620.     else if (daughter_brd_detected == true)
  621.      dev_cfg->device_init(evm_id, profile);
  622.    }
  623.   }
  624. }
  625. }

  626. /* pinmux for usb0 drvvbus */
  627. static struct pinmux_config usb0_pin_mux[] = {
  628. {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0| AM33XX_PIN_OUTPUT},
  629. {NULL, 0},
  630. };
  631. /* pinmux forusb1 drvvbus */
  632. static struct pinmux_config usb1_pin_mux[] = {
  633. {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0| AM33XX_PIN_OUTPUT},
  634. {NULL, 0},
  635. };
  636. /* Module pinmux for eCAP0 */
  637. static struct pinmux_config ecap0_pin_mux[] = {
  638. {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
  639.   OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
  640. {NULL, 0},
  641. };

  642. //#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
  643. //#define AM335XEVM_WLAN_IRQ_GPIO  GPIO_TO_PIN(3, 17)
  644. //#define AM335XEVM_SK_WLAN_IRQ_GPIO     GPIO_TO_PIN(0, 31)
  645. structwl12xx_platform_data am335xevm_wlan_data = {
  646. /*.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
  647. .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
  648. /*.bt_enable_gpio = GPIO_TO_PIN(3, 21),
  649. .wlan_enable_gpio = GPIO_TO_PIN(1, 16),*/
  650. };
  651. static structpinmux_config uart1_wl12xx_pin_mux[] = {
  652. //{"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 |AM33XX_PIN_OUTPUT},
  653. //{"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
  654. {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 |AM33XX_PIN_INPUT_PULLUP},
  655. {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
  656. {NULL, 0},
  657. };
  658. static structpinmux_config wl12xx_pin_mux[] = {
  659. //{"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
  660. //{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 |AM33XX_PIN_INPUT},
  661. //{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 |AM33XX_PIN_OUTPUT_PULLUP},
  662. {NULL, 0},
  663. };
  664. static structpinmux_config wl12xx_pin_mux_sk[] = {
  665. //{"gpmc_wpn.gpio0_31", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
  666. //{"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 |AM33XX_PIN_OUTPUT_PULLUP},
  667. //{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 |AM33XX_PIN_OUTPUT},
  668. {NULL, 0},
  669. };
  670. static boolbacklight_enable;
  671. static voidenable_ecap0(int evm_id, int profile)
  672. {
  673. backlight_enable = true;
  674. setup_pin_mux(ecap0_pin_mux);
  675. }
  676. static voidenable_ecap2(int evm_id, int profile)
  677. {
  678. backlight_enable = true;
  679. //setup_pin_mux(ecap2_pin_mux);
  680. }
  681. /* Setuppwm-backlight */
  682. static struct platform_device am335x_backlight = {
  683. .name           ="pwm-backlight",
  684. .id            = -1,
  685. .dev  = {
  686.   .platform_data = &am335x_backlight_data0,
  687. },
  688. };
  689. static structpwmss_platform_data  pwm_pdata[3] = {
  690. {
  691.   .version = PWM_VERSION_1,
  692. },
  693. {
  694.   .version = PWM_VERSION_1,
  695. },
  696. {
  697.   .version = PWM_VERSION_1,
  698. },
  699. };
  700. static int__init backlight_init(void)
  701. {
  702. int status = 0;
  703. if(backlight_enable) {
  704.   int ecap_index = 0;
  705.   switch(am335x_evm_get_id()) {
  706.   case GEN_PURP_EVM:
  707.   case GEN_PURP_DDR3_EVM:
  708.    ecap_index = 0;
  709.    break;
  710.   case EVM_SK:
  711.    /*
  712.     * Invert polarity of PWM wave from ECAP to handle
  713.     * backlight intensity to pwm brightness
  714.     */
  715.    ecap_index = 2;
  716.    pwm_pdata[ecap_index].chan_attrib[0].inverse_pol = true;
  717.    am335x_backlight.dev.platform_data =
  718.     &am335x_backlight_data2;
  719.    break;
  720.   default:
  721.    pr_err("%s: Error on attempting to enablebacklight,"
  722.     " not supported\n", __func__);
  723.    return -EINVAL;
  724.   }
  725.   am33xx_register_ecap(ecap_index,&pwm_pdata[ecap_index]);
  726.   platform_device_register(&am335x_backlight);
  727. }
  728. return status;
  729. }
  730. late_initcall(backlight_init);
  731. static int__init conf_disp_pll(int rate)
  732. {
  733. struct clk *disp_pll;
  734. int ret = -EINVAL;
  735. disp_pll= clk_get(NULL, "dpll_disp_ck");
  736. if (IS_ERR(disp_pll)) {
  737.   pr_err("Cannot clk_get disp_pll\n");
  738.   goto out;
  739. }
  740. ret =clk_set_rate(disp_pll, rate);
  741. clk_put(disp_pll);
  742. out:
  743. return ret;
  744. }
  745. static voidlcdc_init(int evm_id, int profile)
  746. {
  747. struct da8xx_lcdc_platform_data *lcdc_pdata;
  748. setup_pin_mux(lcdc_pin_mux);

  749. pr_info("lcdc_init ********************************** \n");

  750. if (conf_disp_pll(300000000)) {
  751.   pr_info("Failed configure display PLL, not attempting to"
  752.     "register LCDC\n");
  753.   return;
  754. }
  755. switch (evm_id) {
  756. case GEN_PURP_EVM:
  757. case GEN_PURP_DDR3_EVM:
  758.   lcdc_pdata = &TFC_S9700RTWV35TR_01B_pdata;
  759.   break;
  760. case EVM_SK:
  761.   //lcdc_pdata = &NHD_480272MF_ATXI_pdata;
  762.   lcdc_pdata = &YL_LCD_pdata;
  763.   break;
  764. default:
  765.   pr_err("LCDC not supported on this evm (%d)\n",evm_id);
  766.   return;
  767. }
  768. lcdc_pdata->get_context_loss_count= omap_pm_get_dev_context_loss_count;
  769. if(am33xx_register_lcdc(lcdc_pdata))
  770.   pr_info("Failed to register LCDC device\n");
  771. return;
  772. }

  773. static void mfd_tscadc_init(int evm_id, int profile)
  774. {
  775. int err;

  776. pr_info("mfd_tscadc_init **********************************\n");

  777. err = am33xx_register_mfd_tscadc(&tscadc);
  778. if (err)
  779.   pr_err("failed to register touchscreen device\n");
  780. }
  781. static voidrgmii1_init(int evm_id, int profile)
  782. {
  783. pr_info("rgmii1_init ********************************** \n");
  784. setup_pin_mux(rgmii1_pin_mux);
  785. return;
  786. }
  787. static voidrgmii2_init(int evm_id, int profile)
  788. {
  789. pr_info("rgmii2_init ********************************** \n");
  790. setup_pin_mux(rgmii2_pin_mux);
  791. return;
  792. }
  793. static voidusb0_init(int evm_id, int profile)
  794. {
  795. setup_pin_mux(usb0_pin_mux);
  796. return;
  797. }
  798. static voidusb1_init(int evm_id, int profile)
  799. {
  800. setup_pin_mux(usb1_pin_mux);
  801. return;
  802. }
  803. /* setupuart4 */            //lh
  804. static void uart4_init(int evm_id, int profile)
  805. {
  806. pr_info("uart4_init ********************************** \n");
  807. setup_pin_mux(uart4_pin_mux);
  808. return;
  809. }
  810. /* setupuart3 */
  811. static void uart3_init(int evm_id, int profile)
  812. {
  813. pr_info("uart3_init ********************************** \n");
  814. //setup_pin_mux(uart3_pin_mux);
  815. return;
  816. }
  817. /* setupuart2 */
  818. static void uart2_init(int evm_id, int profile)
  819. {
  820. pr_info("uart2_init ********************************** \n");
  821. //setup_pin_mux(uart2_pin_mux);
  822. return;
  823. }
  824. /*
  825. * gpio0_7 was driven HIGH in u-boot before DDR configuration
  826. *
  827. * setup gpio0_7 for EVM-SK 1.2
  828. */
  829. static void gpio_ddr_vtt_enb_init(int evm_id, int profile)
  830. {
  831. //setup_pin_mux(gpio_ddr_vtt_enb_pin_mux);
  832. return;
  833. }
  834. /* setuphaptics */
  835. #define HAPTICS_MAX_FREQ 250
  836. static void haptics_init(int evm_id, int profile)
  837. {
  838. //setup_pin_mux(haptics_pin_mux);
  839. pwm_pdata[2].chan_attrib[1].max_freq = HAPTICS_MAX_FREQ;
  840. am33xx_register_ehrpwm(2, &pwm_pdata[2]);
  841. }
  842. /* NANDpartition information */
  843. static struct mtd_partition am335x_nand_partitions[] = {
  844. /* All the partition sizes are listed in terms of NAND block size */
  845. {
  846.   .name           ="SPL",
  847.   .offset         =0,   /* Offset = 0x0 */
  848.   .size           =SZ_128K,
  849. },
  850. {
  851.   .name           ="SPL.backup1",
  852.   .offset         =MTDPART_OFS_APPEND, /* Offset = 0x20000 */
  853.   .size           =SZ_128K,
  854. },
  855. {
  856.   .name           ="SPL.backup2",
  857.   .offset         = MTDPART_OFS_APPEND, /*Offset = 0x40000 */
  858.   .size           =SZ_128K,
  859. },
  860. {
  861.   .name           ="SPL.backup3",
  862.   .offset         =MTDPART_OFS_APPEND, /* Offset = 0x60000 */
  863.   .size           =SZ_128K,
  864. },
  865. {
  866.   .name           ="U-Boot",
  867.   .offset         =MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
  868.   .size           =15 * SZ_128K,
  869. },
  870. {
  871.   .name           ="U-Boot Env",
  872.   .offset         =MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
  873.   .size           =1 * SZ_128K,
  874. },
  875. {
  876.   .name           ="Kernel",
  877.   .offset         =MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
  878.   .size           =40 * SZ_128K,
  879. },
  880. {
  881.   .name           ="File System",
  882.   .offset         =MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
  883.   .size           =MTDPART_SIZ_FULL,
  884. },
  885. };
  886. /* SPI 0/1Platform Data */
  887. /* SPI flash information */
  888. static struct mtd_partition am335x_spi_partitions[] = {
  889. /* All the partition sizes are listed in terms of erase size */
  890. {
  891.   .name       = "SPL",
  892.   .offset     = 0,   /* Offset =0x0 */
  893.   .size       = SZ_128K,
  894. },
  895. {
  896.   .name       = "U-Boot",
  897.   .offset     = MTDPART_OFS_APPEND, /*Offset = 0x20000 */
  898.   .size       = (3 * SZ_128K) - SZ_4K,
  899. },
  900. {
  901.   .name       = "U-Boot Env",
  902.   .offset     = MTDPART_OFS_APPEND, /*Offset = 0x7F000 */
  903.   .size       = SZ_4K,
  904. },
  905. {
  906.   .name       = "Kernel",
  907.   .offset     = MTDPART_OFS_APPEND, /*Offset = 0x80000 */
  908.   .size       = 866 *SZ_4K,  /* size = 0x362000 */
  909. },
  910. {
  911.   .name       = "FileSystem",
  912.   .offset     = MTDPART_OFS_APPEND, /*Offset = 0x3E2000 */
  913.   .size       =MTDPART_SIZ_FULL,  /* size ~= 4.1 MiB */
  914. }
  915. };
  916. static conststruct flash_platform_data am335x_spi_flash = {
  917. .type      = "w25q64",
  918. .name      = "spi_flash",
  919. .parts     = am335x_spi_partitions,
  920. .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
  921. };
  922. static structgpmc_timings am335x_nand_timings = {
  923. .sync_clk = 0,
  924. .cs_on= 0,
  925. .cs_rd_off = 44,
  926. .cs_wr_off = 44,
  927. .adv_on= 6,
  928. .adv_rd_off = 34,
  929. .adv_wr_off = 44,
  930. .we_off = 40,
  931. .oe_off = 54,
  932. .access= 64,
  933. .rd_cycle = 82,
  934. .wr_cycle = 82,
  935. .wr_access= 40,
  936. .wr_data_mux_bus = 0,
  937. };
  938. static voidevm_nand_init(int evm_id, int profile)
  939. {
  940. struct omap_nand_platform_data *pdata;
  941. struct gpmc_devices_info gpmc_device[2] = {
  942.   { NULL, 0 },
  943.   { NULL, 0 },
  944. };

  945. pr_info("evm_nand_init ********************************** \n");

  946. setup_pin_mux(nand_pin_mux);
  947. pdata = omap_nand_init(am335x_nand_partitions,
  948.   ARRAY_SIZE(am335x_nand_partitions), 0, 0,
  949.   &am335x_nand_timings);
  950. if (!pdata)
  951.   return;
  952. pdata->ecc_opt =OMAP_ECC_BCH8_CODE_HW;
  953. pdata->elm_used = true;
  954. gpmc_device[0].pdata = pdata;
  955. gpmc_device[0].flag = GPMC_DEVICE_NAND;
  956. omap_init_gpmc(gpmc_device,sizeof(gpmc_device));
  957. omap_init_elm();
  958. }
  959. /* TPS65217voltage regulator support */
  960. /* 1.8V */
  961. static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
  962. {
  963.   .supply = "vdds_osc",
  964. },
  965. {
  966.   .supply = "vdds_pll_ddr",
  967. },
  968. {
  969.   .supply = "vdds_pll_mpu",
  970. },
  971. {
  972.   .supply = "vdds_pll_core_lcd",
  973. },
  974. {
  975.   .supply = "vdds_sram_mpu_bb",
  976. },
  977. {
  978.   .supply = "vdds_sram_core_bg",
  979. },
  980. {
  981.   .supply = "vdda_usb0_1p8v",
  982. },
  983. {
  984.   .supply = "vdds_ddr",
  985. },
  986. {
  987.   .supply = "vdds",
  988. },
  989. {
  990.   .supply = "vdds_hvx_1p8v",
  991. },
  992. {
  993.   .supply = "vdda_adc",
  994. },
  995. {
  996.   .supply = "ddr2",
  997. },
  998. };
  999. /* 1.1V */
  1000. static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
  1001. {
  1002.   .supply = "vdd_mpu",
  1003. },
  1004. };
  1005. /* 1.1V */
  1006. static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
  1007. {
  1008.   .supply = "vdd_core",
  1009. },
  1010. };
  1011. /* 1.8V LDO*/
  1012. static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
  1013. {
  1014.   .supply = "vdds_rtc",
  1015. },
  1016. };
  1017. /* 3.3V LDO*/
  1018. static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
  1019. {
  1020.   .supply = "vdds_any_pn",
  1021. },
  1022. };
  1023. /* 3.3V LDO*/
  1024. static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
  1025. {
  1026.   .supply = "vdds_hvx_ldo3_3p3v",
  1027. },
  1028. {
  1029.   .supply = "vdda_usb0_3p3v",
  1030. },
  1031. };
  1032. /* 3.3V LDO*/
  1033. static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
  1034. {
  1035.   .supply = "vdds_hvx_ldo4_3p3v",
  1036. },
  1037. };
  1038. /*
  1039. * FIXME: Some BeagleBones reuire a ramp_delay to settle down the set
  1040. * voltage from 0.95v to 1.25v. By default a minimum of 70msec is set
  1041. * based on experimentation. This will be removed/modified to exact
  1042. * value, once the root cause is known.
  1043. *
  1044. * The reason for extended ramp time requirement on BeagleBone is not
  1045. * known and the delay varies from board - board, if the board hangs
  1046. * with this 70msec delay then try to increase the value.
  1047. */
  1048. static struct tps65217_rdelay dcdc2_ramp_delay = {
  1049. .ramp_delay = 70000,
  1050. };
  1051. static structregulator_init_data tps65217_regulator_data[] = {
  1052. /* dcdc1 */
  1053. {
  1054.   .constraints = {
  1055.    .min_uV = 900000,
  1056.    .max_uV = 1800000,
  1057.    .boot_on = 1,
  1058.    .always_on = 1,
  1059.   },
  1060.   .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
  1061.   .consumer_supplies = tps65217_dcdc1_consumers,
  1062. },
  1063. /*dcdc2 */
  1064. {
  1065.   .constraints = {
  1066.    .min_uV = 900000,
  1067.    .max_uV = 3300000,
  1068.    .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
  1069.     REGULATOR_CHANGE_STATUS),
  1070.    .boot_on = 1,
  1071.    .always_on = 1,
  1072.   },
  1073.   .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
  1074.   .consumer_supplies = tps65217_dcdc2_consumers,
  1075.   .driver_data = &dcdc2_ramp_delay,
  1076.   .ignore_check_consumers = 1,
  1077. },
  1078. /*dcdc3 */
  1079. {
  1080.   .constraints = {
  1081.    .min_uV = 900000,
  1082.    .max_uV = 1500000,
  1083.    .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
  1084.     REGULATOR_CHANGE_STATUS),
  1085.    .boot_on = 1,
  1086.    .always_on = 1,
  1087.   },
  1088.   .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
  1089.   .consumer_supplies = tps65217_dcdc3_consumers,
  1090.   .ignore_check_consumers = 1,
  1091. },
  1092. /* ldo1*/
  1093. {
  1094.   .constraints = {
  1095.    .min_uV = 1000000,
  1096.    .max_uV = 3300000,
  1097.    .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  1098.    .boot_on = 1,
  1099.    .always_on = 1,
  1100.   },
  1101.   .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
  1102.   .consumer_supplies = tps65217_ldo1_consumers,
  1103. },
  1104. /* ldo2*/
  1105. {
  1106.   .constraints = {
  1107.    .min_uV = 900000,
  1108.    .max_uV = 3300000,
  1109.    .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
  1110.     REGULATOR_CHANGE_STATUS),
  1111.    .boot_on = 1,
  1112.    .always_on = 1,
  1113.   },
  1114.   .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
  1115.   .consumer_supplies = tps65217_ldo2_consumers,
  1116. },
  1117. /* ldo3*/
  1118. {
  1119.   .constraints = {
  1120.    .min_uV = 1800000,
  1121.    .max_uV = 3300000,
  1122.    .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
  1123.     REGULATOR_CHANGE_STATUS),
  1124.    .boot_on = 1,
  1125.    .always_on = 1,
  1126.   },
  1127.   .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
  1128.   .consumer_supplies = tps65217_ldo3_consumers,
  1129. },
  1130. /* ldo4*/
  1131. {
  1132.   .constraints = {
  1133.    .min_uV = 1800000,
  1134.    .max_uV = 3300000,
  1135.    .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
  1136.     REGULATOR_CHANGE_STATUS),
  1137.    .boot_on = 1,
  1138.    .always_on = 1,
  1139.   },
  1140.   .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
  1141.   .consumer_supplies = tps65217_ldo4_consumers,
  1142. },
  1143. };
  1144. static structtps65217_board beaglebone_tps65217_info = {
  1145. .tps65217_init_data = &tps65217_regulator_data[0],
  1146. .status_off = true,
  1147. };

  1148. static struct i2c_board_infoam335x_i2c1_boardinfo[]= {
  1149. #if 0
  1150. {
  1151.   I2C_BOARD_INFO("tlv320aic3x",0x1b),
  1152. },
  1153.         
  1154. {
  1155.   I2C_BOARD_INFO("tsl2550",0x39),
  1156. },
  1157. {
  1158.   I2C_BOARD_INFO("tmp275",0x48),
  1159. },
  1160. #endif
  1161. };
  1162. static void i2c1_init(int evm_id, int profile)
  1163. {
  1164. //setup_pin_mux(i2c1_pin_mux);
  1165. omap_register_i2c_bus(2,100, am335x_i2c1_boardinfo,
  1166.    ARRAY_SIZE(am335x_i2c1_boardinfo));
  1167. return;
  1168. }
  1169. static structi2c_board_info am335x_i2c2_boardinfo[] = {
  1170. };
  1171. static void i2c2_init(int evm_id, int profile)
  1172. {
  1173. //setup_pin_mux(i2c2_pin_mux);
  1174. omap_register_i2c_bus(3,100, am335x_i2c2_boardinfo,
  1175.    ARRAY_SIZE(am335x_i2c2_boardinfo));
  1176. return;
  1177. }
  1178. /* SetupMcASP 1 */
  1179. static void mcasp1_init(int evm_id, int profile)
  1180. {
  1181. pr_info("--------mcasp1_init\n");
  1182. /* Configure McASP */
  1183. setup_pin_mux(mcasp1_pin_mux);
  1184. switch (evm_id) {
  1185. case EVM_SK:
  1186.   pr_info("--------evm_id is SK\n");
  1187.   am335x_register_mcasp(&am335x_evm_sk_snd_data1,1);
  1188.   break;
  1189. default:
  1190.   am335x_register_mcasp(&am335x_evm_snd_data1,1);
  1191. }
  1192. return;
  1193. }
  1194. static voidmmc1_init(int evm_id, int profile)
  1195. {
  1196. /*setup_pin_mux(mmc1_common_pin_mux);
  1197. setup_pin_mux(mmc1_dat4_7_pin_mux);
  1198. setup_pin_mux(mmc1_wp_only_pin_mux);
  1199. setup_pin_mux(mmc1_cd_only_pin_mux);
  1200. am335x_mmc[1].mmc= 2;
  1201. am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
  1202. am335x_mmc[1].gpio_cd = GPIO_TO_PIN(1, 28);//--czx
  1203. am335x_mmc[1].gpio_wp = -EINVAL;//GPIO_TO_PIN(1, 29);
  1204. am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
  1205. /* mmcwill be initialized when mmc0_init is called */
  1206. return;
  1207. }
  1208. static voidmmc1_wl12xx_init(int evm_id, int profile)
  1209. {
  1210. /*setup_pin_mux(mmc1_common_pin_mux);
  1211. am335x_mmc[1].mmc = 2;
  1212. am335x_mmc[1].name = "wl1271";
  1213. am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
  1214. am335x_mmc[1].nonremovable = true;
  1215. am335x_mmc[1].pm_caps = MMC_PM_KEEP_POWER;
  1216. am335x_mmc[1].gpio_cd = -EINVAL;
  1217. am335x_mmc[1].gpio_wp = -EINVAL;
  1218. am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
  1219. }
  1220. static voidmmc1_emmc_init(int evm_id, int profile)
  1221. {
  1222. /*setup_pin_mux(mmc1_common_pin_mux);
  1223. setup_pin_mux(mmc1_dat4_7_pin_mux);
  1224. am335x_mmc[1].mmc= 2;
  1225. am335x_mmc[1].caps = MMC_CAP_8_BIT_DATA;
  1226. am335x_mmc[1].gpio_cd = -EINVAL;
  1227. am335x_mmc[1].gpio_wp = -EINVAL;
  1228. am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
  1229. /* mmcwill be initialized when mmc0_init is called */
  1230. return;
  1231. }
  1232. static voidmmc2_wl12xx_init(int evm_id, int profile)
  1233. {
  1234. /*setup_pin_mux(mmc2_wl12xx_pin_mux);
  1235. am335x_mmc[1].mmc= 3;
  1236. am335x_mmc[1].name = "wl1271";
  1237. am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
  1238. am335x_mmc[1].nonremovable = true;
  1239. am335x_mmc[1].gpio_cd = -EINVAL;
  1240. am335x_mmc[1].gpio_wp = -EINVAL;
  1241. am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
  1242. /* mmcwill be initialized when mmc0_init is called */
  1243. return;
  1244. }
  1245. static voiduart1_wl12xx_init(int evm_id, int profile)
  1246. {
  1247. setup_pin_mux(uart1_wl12xx_pin_mux);
  1248. }
  1249. static voidwl12xx_bluetooth_enable(void)
  1250. {
  1251. int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
  1252.   "bt_en\n");
  1253. if (status < 0)
  1254.   pr_err("Failed to request gpio for bt_enable");
  1255. pr_info("ConfigureBluetooth Enable pin...\n");
  1256. gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
  1257. }
  1258. #defineAM33XX_CTRL_REGADDR(reg)     \
  1259.   AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
  1260. /* wlanenable pin */
  1261. #define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET  0x087C
  1262. static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
  1263. {
  1264. int pad_mux_value;
  1265. if (on){
  1266.   gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 1);
  1267.   /*Enable pullup on the WLAN enable pin for keeping wlan active during suspend
  1268.      in wowlan mode */
  1269.   if ( am335x_evm_get_id() == EVM_SK ) {
  1270.    pad_mux_value = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
  1271.    pad_mux_value &= (~AM33XX_PULL_DISA);
  1272.    writel(pad_mux_value,AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
  1273.   }
  1274.   mdelay(70);
  1275. } else {
  1276.   gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 0);
  1277.   /* Disable pullup on the WLAN enable when WLAN is off */
  1278.   if ( am335x_evm_get_id() == EVM_SK ) {
  1279.    pad_mux_value =readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
  1280.    pad_mux_value |= AM33XX_PULL_DISA;
  1281.    writel(pad_mux_value, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
  1282.   }
  1283. }
  1284. return0;
  1285. }
  1286. static voidd_can_init(int evm_id, int profile)
  1287. {
  1288. switch (evm_id) {
  1289. case IND_AUT_MTR_EVM:
  1290.   if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
  1291.    setup_pin_mux(d_can_gp_pin_mux);
  1292.    /* Instance Zero */
  1293.    am33xx_d_can_init(0);
  1294.   }
  1295.   break;
  1296. case GEN_PURP_EVM:
  1297. case GEN_PURP_DDR3_EVM:
  1298.   if (profile == PROFILE_1) {
  1299.    setup_pin_mux(d_can_gp_pin_mux);
  1300.    /* Instance One */
  1301.    am33xx_d_can_init(1);
  1302.   }
  1303.   break;
  1304. default:
  1305.   break;
  1306. }
  1307. }
  1308. static voidmmc0_init(int evm_id, int profile)
  1309. {
  1310. switch (evm_id) {
  1311. case BEAGLE_BONE_A3:
  1312. case BEAGLE_BONE_OLD:
  1313. case EVM_SK:
  1314.   setup_pin_mux(mmc0_common_pin_mux);
  1315.   //setup_pin_mux(mmc0_cd_only_pin_mux);
  1316.   break;
  1317. default:
  1318.   setup_pin_mux(mmc0_common_pin_mux);
  1319.   //setup_pin_mux(mmc0_cd_only_pin_mux);
  1320.   
  1321.   break;
  1322. }
  1323. omap2_hsmmc_init(am335x_mmc);
  1324. return;
  1325. }
  1326. static structi2c_board_info tps65217_i2c_boardinfo[] = {
  1327. {
  1328.   I2C_BOARD_INFO("tps65217",TPS65217_I2C_ID),
  1329.   .platform_data  = &beaglebone_tps65217_info,
  1330. },
  1331. };
  1332. static voidtps65217_init(int evm_id, int profile)
  1333. {
  1334. struct i2c_adapter*adapter;
  1335. struct i2c_client*client;
  1336. struct device *mpu_dev;
  1337. struct tps65217 *tps;
  1338. unsigned int val;
  1339. int ret;
  1340. mpu_dev= omap_device_get_by_hwmod_name("mpu");
  1341. if (!mpu_dev)
  1342.   pr_warning("%s: unable to get the mpu device\n",__func__);
  1343. /* I2C1 adapter request */
  1344. adapter = i2c_get_adapter(1);
  1345. if (!adapter) {
  1346.   pr_err("failed to get adapter i2c1\n");
  1347.   return;
  1348. }
  1349. client= i2c_new_device(adapter,tps65217_i2c_boardinfo);
  1350. if (!client)
  1351.   pr_err("failed to register tps65217 to i2c1\n");
  1352. i2c_put_adapter(adapter);
  1353. tps =(struct tps65217 *)i2c_get_clientdata(client);
  1354. ret =tps65217_reg_read(tps, TPS65217_REG_STATUS, &val);
  1355. if (ret) {
  1356.   pr_err("failed to read tps65217 status reg\n");
  1357.   return;
  1358. }
  1359. if(!(val & TPS65217_STATUS_ACPWR)) {
  1360.   /* If powered by USB then disable OPP120 and OPPTURBO */
  1361.   pr_info("Maximum current provided by the USB port is500mA"
  1362.    " which is not sufficient\nwhen operating @OPP120and"
  1363.    " OPPTURBO. The current requirement forsome\nuse-cases"
  1364.    " using OPP100 might also exceed the maximumcurrent"
  1365.    " that the\nUSB port can provide. Unless you arefully"
  1366.    " confident that the current\nrequirements forOPP100"
  1367.    " use-case don't exceed the USB limits,switching\nto"
  1368.    " AC power is recommended.\n");
  1369.   opp_disable(mpu_dev, 600000000);
  1370.   opp_disable(mpu_dev, 720000000);
  1371. }
  1372. }
  1373. static voidmmc0_no_cd_init(int evm_id, int profile)
  1374. {
  1375. setup_pin_mux(mmc0_common_pin_mux);

  1376. omap2_hsmmc_init(am335x_mmc);
  1377. return;
  1378. }
  1379. /* ConfigureGPIOs for GPIO Keys */
  1380. static struct gpio_keys_button am335x_evm_gpio_buttons[] = {
  1381. { //K1 --czx
  1382.   .code                  = BTN_0,
  1383.   .gpio                  = GPIO_TO_PIN(3, 14),
  1384.   .desc                  = "SW1",
  1385. },
  1386. { //K2
  1387.   .code                  = BTN_1,
  1388.   .gpio                  = GPIO_TO_PIN(3, 15),
  1389.   .desc                  = "SW2",
  1390. },
  1391. { //K3
  1392.   .code                  = BTN_2,
  1393.   .gpio                  = GPIO_TO_PIN(3, 16),
  1394.   .desc                  = "SW3",
  1395.   .wakeup                = 1,
  1396. },
  1397. { //K4
  1398.   .code                  = BTN_3,
  1399.   .gpio                  = GPIO_TO_PIN(3, 18),
  1400.   .desc                  = "SW4",
  1401. },
  1402. };
  1403. static structgpio_keys_platform_data am335x_evm_gpio_key_info = {
  1404. .buttons        = am335x_evm_gpio_buttons,
  1405. .nbuttons       =ARRAY_SIZE(am335x_evm_gpio_buttons),
  1406. };
  1407. static structplatform_device am335x_evm_gpio_keys = {
  1408. .name   = "gpio-keys",
  1409. .id     = -1,
  1410. .dev    = {
  1411.   .platform_data  = &am335x_evm_gpio_key_info,
  1412. },
  1413. };
  1414. static voidgpio_keys_init(int evm_id, int profile)
  1415. {
  1416. int err;

  1417. pr_info("gpio_keys_init **********************************\n");

  1418. setup_pin_mux(gpio_keys_pin_mux);
  1419. err = platform_device_register(&am335x_evm_gpio_keys);
  1420. if (err)
  1421.   pr_err("failed to register gpio key device\n");
  1422. }
  1423. static structgpio_led gpio_leds[] = {
  1424. {
  1425.   .name   = "am335x:EVM_SK:usr0",
  1426.   .gpio   = GPIO_TO_PIN(1, 30), /* D1 */ //--czx
  1427. },
  1428. {
  1429.   .name   = "am335x:EVM_SK:usr1",
  1430.   .gpio   = GPIO_TO_PIN(1, 31), /* D2 */ //--czx
  1431.   .default_trigger = "heartbeat",
  1432. },
  1433. };
  1434. static structgpio_led_platform_data gpio_led_info = {
  1435. .leds  = gpio_leds,
  1436. .num_leds = ARRAY_SIZE(gpio_leds),
  1437. };
  1438. static structplatform_device leds_gpio = {
  1439. .name = "leds-gpio",
  1440. .id = -1,
  1441. .dev = {
  1442.   .platform_data = &gpio_led_info,
  1443. },
  1444. };
  1445. static voidgpio_led_init(int evm_id, int profile)
  1446. {
  1447. int err;
  1448. pr_info("gpio_led_init ********************************** \n");
  1449. setup_pin_mux(gpio_led_mux);
  1450. err = platform_device_register(&leds_gpio);
  1451. if (err)
  1452.   pr_err("failed to register gpio led device\n");
  1453. }

  1454. static void profibus_init(intevm_id, int profile)
  1455. {
  1456. //setup_pin_mux(profibus_pin_mux);
  1457. return;
  1458. }
  1459. static structomap_rtc_pdata am335x_rtc_info = {
  1460. .pm_off  = false,
  1461. .wakeup_capable = 0,
  1462. };
  1463. static voidam335x_rtc_init(int evm_id, int profile)
  1464. {
  1465. void __iomem *base;
  1466. struct clk *clk;
  1467. struct omap_hwmod *oh;
  1468. struct platform_device *pdev;
  1469. char *dev_name = "am33xx-rtc";
  1470. clk =clk_get(NULL, "rtc_fck");
  1471. if (IS_ERR(clk)) {
  1472.   pr_err("rtc : Failed to get RTC clock\n");
  1473.   return;
  1474. }
  1475. if(clk_enable(clk)) {
  1476.   pr_err("rtc: Clock Enable Failed\n");
  1477.   return;
  1478. }
  1479. base =ioremap(AM33XX_RTC_BASE, SZ_4K);
  1480. if(WARN_ON(!base))
  1481.   return;
  1482. /*Unlock the rtc's registers */
  1483. writel(0x83e70b13, base + 0x6c);
  1484. writel(0x95a4f1e0, base + 0x70);
  1485. /*
  1486.   * Enable the 32K OSc
  1487.   * TODO: Need a better way to handle this
  1488.   * Since we want the clock to be running before mmc init
  1489.   * we need to do it before the rtc probe happens
  1490.   */
  1491. writel(0x48, base + 0x54);
  1492. iounmap(base);
  1493. switch(evm_id) {
  1494. case BEAGLE_BONE_A3:
  1495. case BEAGLE_BONE_OLD:
  1496.   am335x_rtc_info.pm_off = true;
  1497.   break;
  1498. default:
  1499.   break;
  1500. }
  1501. clk_disable(clk);
  1502. clk_put(clk);
  1503. if(omap_rev() >= AM335X_REV_ES2_0)
  1504.   am335x_rtc_info.wakeup_capable = 1;
  1505. oh =omap_hwmod_lookup("rtc");
  1506. if (!oh) {
  1507.   pr_err("could not look up %s\n", "rtc");
  1508.   return;
  1509. }
  1510. pdev =omap_device_build(dev_name, -1, oh, &am335x_rtc_info,
  1511.    sizeof(struct omap_rtc_pdata), NULL, 0, 0);
  1512. WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
  1513.    dev_name, oh->name);
  1514. }
  1515. /* Enableclkout2 */
  1516. static struct pinmux_config clkout2_pin_mux[] = {
  1517. //{"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 |AM33XX_PIN_OUTPUT},
  1518. {NULL, 0},
  1519. };
  1520. static voidclkout2_enable(int evm_id, int profile)
  1521. {
  1522. struct clk *ck_32;
  1523. ck_32 =clk_get(NULL, "clkout2_ck");
  1524. if (IS_ERR(ck_32)) {
  1525.   pr_err("Cannot clk_get ck_32\n");
  1526.   return;
  1527. }
  1528. clk_enable(ck_32);
  1529. setup_pin_mux(clkout2_pin_mux);
  1530. }
  1531. static voidsgx_init(int evm_id, int profile)
  1532. {
  1533. if (omap3_has_sgx()) {
  1534.   am33xx_gpu_init();
  1535. }
  1536. }
  1537. /* General Purpose EVM */
  1538. /*static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
  1539. {am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1540. {clkout2_enable, DEV_ON_BASEBOARD, PROFILE_ALL},
  1541. {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
  1542.       PROFILE_2 | PROFILE_7) },
  1543. {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
  1544.       PROFILE_2 | PROFILE_7) },
  1545. {mfd_tscadc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
  1546.       PROFILE_2 | PROFILE_7) },
  1547. {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1548. {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
  1549.       PROFILE_4 | PROFILE_6) },
  1550. {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1551. {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1552. {evm_nand_init, DEV_ON_DGHTR_BRD,
  1553.   (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
  1554. {i2c1_init,    DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
  1555. {lis331dlh_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
  1556. {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 |PROFILE_7)},
  1557. {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
  1558. {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
  1559.         PROFILE_5)},
  1560. {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
  1561. {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
  1562. {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
  1563. {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
  1564.         PROFILE_5)},
  1565. {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |PROFILE_5)},
  1566. {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
  1567. {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
  1568. {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
  1569. {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
  1570. {haptics_init, DEV_ON_DGHTR_BRD, (PROFILE_4)},
  1571. {sgx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1572. {NULL, 0, 0},
  1573. };
  1574. */

  1575. /* EVM - Starter Kit */
  1576. static struct evm_dev_cfg evm_sk_dev_cfg[] = {
  1577. {am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1578. {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
  1579. //{spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},//--czx
  1580. {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
  1581. {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
  1582. {mmc0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1583. //{mmc1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1584. {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1585. {rgmii2_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1586. {lcdc_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
  1587. {enable_ecap0,     DEV_ON_BASEBOARD,PROFILE_ALL},//--lh
  1588. {mfd_tscadc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1589. {gpio_keys_init,  DEV_ON_BASEBOARD, PROFILE_ALL},
  1590. {gpio_led_init,  DEV_ON_BASEBOARD, PROFILE_ALL},
  1591. //{lis331dlh_init, DEV_ON_BASEBOARD, PROFILE_ALL}, //--lh
  1592. {mcasp1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
  1593. {uart4_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
  1594. // {uart1_wl12xx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1595. // {wl12xx_init,       DEV_ON_BASEBOARD,PROFILE_ALL},
  1596. //{gpio_ddr_vtt_enb_init, DEV_ON_BASEBOARD, PROFILE_ALL},
  1597. {sgx_init,       DEV_ON_BASEBOARD,PROFILE_ALL},

  1598. {NULL, 0, 0},
  1599. };
  1600. static intam33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
  1601. {
  1602. phy_write(phydev, AR8051_PHY_DEBUG_ADDR_REG,
  1603.     AR8051_DEBUG_RGMII_CLK_DLY_REG);
  1604. phy_write(phydev, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY);
  1605. return0;
  1606. }
  1607. #defineAM33XX_VDD_CORE_OPP50_UV  1100000
  1608. #define AM33XX_OPP120_FREQ  600000000
  1609. #define AM33XX_OPPTURBO_FREQ  720000000
  1610. #define AM33XX_ES2_0_VDD_CORE_OPP50_UV 950000
  1611. #define AM33XX_ES2_0_OPP120_FREQ 720000000
  1612. #define AM33XX_ES2_0_OPPTURBO_FREQ 800000000
  1613. #define AM33XX_ES2_0_OPPNITRO_FREQ 1000000000
  1614. #defineAM33XX_ES2_1_VDD_CORE_OPP50_UV 950000
  1615. #define AM33XX_ES2_1_OPP120_FREQ 720000000
  1616. #define AM33XX_ES2_1_OPPTURBO_FREQ 800000000
  1617. #define AM33XX_ES2_1_OPPNITRO_FREQ 1000000000
  1618. static voidam335x_opp_update(void)
  1619. {
  1620. u32 rev;
  1621. int voltage_uv = 0;
  1622. struct device *core_dev, *mpu_dev;
  1623. struct regulator *core_reg;
  1624. core_dev= omap_device_get_by_hwmod_name("l3_main");
  1625. mpu_dev = omap_device_get_by_hwmod_name("mpu");
  1626. if(!mpu_dev || !core_dev) {
  1627.   pr_err("%s: Aiee.. no mpu/core devices? %p %p\n",__func__,
  1628.          mpu_dev, core_dev);
  1629.   return;
  1630. }
  1631. core_reg= regulator_get(core_dev, "vdd_core");
  1632. if (IS_ERR(core_reg)) {
  1633.   pr_err("%s: unable to get core regulator\n", __func__);
  1634.   return;
  1635. }
  1636. /*
  1637.   * Ensure physical regulator is present.
  1638.   * (e.g. could be dummy regulator.)
  1639.   */
  1640. voltage_uv = regulator_get_voltage(core_reg);
  1641. if (voltage_uv < 0) {
  1642.   pr_err("%s: physical regulator not present for core" \
  1643.          "(%d)\n", __func__,voltage_uv);
  1644.   regulator_put(core_reg);
  1645.   return;
  1646. }
  1647. pr_debug("%s:core regulator value %d\n", __func__, voltage_uv);
  1648. if (voltage_uv > 0) {
  1649.   rev = omap_rev();
  1650.   switch (rev) {
  1651.   case AM335X_REV_ES1_0:
  1652.    if (voltage_uv <= AM33XX_VDD_CORE_OPP50_UV) {
  1653.     /*
  1654.      * disable the higher freqs - we dont care about
  1655.      * the results
  1656.      */
  1657.     opp_disable(mpu_dev, AM33XX_OPP120_FREQ);
  1658.     opp_disable(mpu_dev, AM33XX_OPPTURBO_FREQ);
  1659.    }
  1660.    break;
  1661.   case AM335X_REV_ES2_0:
  1662.    if (voltage_uv <= AM33XX_ES2_0_VDD_CORE_OPP50_UV) {
  1663.     /*
  1664.      * disable the higher freqs - we dont care about
  1665.      * the results
  1666.      */
  1667.     opp_disable(mpu_dev,
  1668.          AM33XX_ES2_0_OPP120_FREQ);
  1669.     opp_disable(mpu_dev,
  1670.          AM33XX_ES2_0_OPPTURBO_FREQ);
  1671.     opp_disable(mpu_dev,
  1672.          AM33XX_ES2_0_OPPNITRO_FREQ);
  1673.    }
  1674.    break;
  1675.   case AM335X_REV_ES2_1:
  1676.   /* FALLTHROUGH */
  1677.   default:
  1678.    if (voltage_uv <= AM33XX_ES2_1_VDD_CORE_OPP50_UV) {
  1679.     /*
  1680.      * disable the higher freqs - we dont care about
  1681.      * the results
  1682.      */
  1683.     opp_disable(mpu_dev,
  1684.          AM33XX_ES2_1_OPP120_FREQ);
  1685.     opp_disable(mpu_dev,
  1686.          AM33XX_ES2_1_OPPTURBO_FREQ);
  1687.     opp_disable(mpu_dev,
  1688.          AM33XX_ES2_1_OPPNITRO_FREQ);
  1689.    }
  1690.    break;
  1691.   }
  1692. }
  1693. }
  1694. /*
  1695. static void setup_general_purpose_evm(void)
  1696. {
  1697. u32 prof_sel = am335x_get_profile_selection();
  1698. u32 boardid = GEN_PURP_EVM;

  1699. pr_info("setup_general_purpose_evm********************************** \n");

  1700. if (!strncmp("1.5A",config.version, 4))
  1701.   boardid = GEN_PURP_DDR3_EVM;
  1702. pr_info("Theboard is general purpose EVM %sin profile %d\n",
  1703.    ((boardid == GEN_PURP_DDR3_EVM) ? "with DDR3 " :""),
  1704.    prof_sel);
  1705. _configure_device(boardid,gen_purp_evm_dev_cfg, (1L<< prof_sel));
  1706. am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII,NULL, NULL);
  1707. /* Atheros Tx Clk delay Phy fixup */
  1708. /*phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
  1709.        am33xx_evm_tx_clk_dly_phy_fixup);
  1710. }
  1711. */
  1712. /* EVM -Starter Kit */
  1713. static void setup_starterkit(void)
  1714. {
  1715. pr_info("The board is a AM335x Starter Kit.\n");
  1716. /*Starter Kit has Micro-SD slot which doesn't have Write Protect pin */
  1717. am335x_mmc[0].gpio_wp = -EINVAL;
  1718. _configure_device(EVM_SK,evm_sk_dev_cfg, PROFILE_NONE);

  1719. am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);
  1720. /* Atheros Tx Clk delay Phy fixup */
  1721. phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
  1722.        am33xx_evm_tx_clk_dly_phy_fixup);
  1723. }
  1724. static voidam335x_setup_daughter_board(struct memory_accessor *m, void *c)
  1725. {
  1726. int ret;
  1727. /*
  1728.   * Read from the EEPROM to see the presence of daughter board.
  1729.   * If present, print the cpld version.
  1730.   */
  1731. ret =m->read(m, (char *)&config1, 0, sizeof(config1));
  1732. if (ret == sizeof(config1)) {
  1733.   pr_info("Detected a daughter card on AM335x EVM..");
  1734.   daughter_brd_detected = true;
  1735. }
  1736.   else {
  1737.   pr_info("No daughter card found\n");
  1738.   daughter_brd_detected = false;
  1739.   return;
  1740. }
  1741. if(!strncmp("CPLD", config1.cpld_ver, 4))
  1742.   pr_info("CPLD version: %s\n", config1.cpld_ver);
  1743. else
  1744.   pr_err("Unknown CPLD version found\n");
  1745. }
  1746. static voidam335x_evm_setup(struct memory_accessor *mem_acc, void *context)
  1747. {
  1748. int ret;
  1749. char tmp[10];

  1750. pr_info("am335x_evm_setup **********************************\n");
  1751.   
  1752. /* 1st get the MAC address from EEPROM */
  1753. am335x_mac_addr[0][0]= 0x00;
  1754. am335x_mac_addr[0][1] = 0x22;
  1755. am335x_mac_addr[0][2] = 0x15;
  1756. am335x_mac_addr[0][3] = 0x00;
  1757. am335x_mac_addr[0][4] = 0x00;
  1758. am335x_mac_addr[0][5] = 0x01;

  1759. am335x_mac_addr[1][0] = 0x00;
  1760. am335x_mac_addr[1][1] = 0x22;
  1761. am335x_mac_addr[1][2] = 0x15;
  1762. am335x_mac_addr[1][3] = 0x00;
  1763. am335x_mac_addr[1][4] = 0x00;
  1764. am335x_mac_addr[1][5] = 0x02;

  1765. am335x_mac_addr[2][0] = 0x00;
  1766. am335x_mac_addr[2][1] = 0x22;
  1767. am335x_mac_addr[2][2] = 0x15;
  1768. am335x_mac_addr[2][3] = 0x00;
  1769. am335x_mac_addr[2][4] = 0x00;
  1770. am335x_mac_addr[2][5] = 0x02;
  1771. /*Fillup global mac id */
  1772. am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
  1773.     &am335x_mac_addr[1][0]);
  1774. config.header= 0xEE3355AA;
  1775. memcpy(config.name,"A335X_SK",8);
  1776. memcpy(config.version,"V1.0",4);
  1777. memcpy(config.opt,"SKU#01",6);
  1778. snprintf(tmp,sizeof(config.name) + 1, "%s", config.name);
  1779. pr_info("Board name: %s\n", tmp);
  1780. snprintf(tmp, sizeof(config.version) + 1, "%s",config.version);
  1781. pr_info("Board version: %s\n", tmp);
  1782. daughter_brd_detected= false;
  1783. setup_starterkit();  
  1784. am335x_opp_update();
  1785. /*
  1786.   * For now, Beaglebone Black uses PG 2.0 that are speed binned andoperate
  1787.   * up to 1GHz. So re-enable Turbo and Nitro modes,
  1788.   */
  1789. if (!strncmp("A335BNLT", config.name, 8)) {
  1790.   struct device *mpu_dev;
  1791.   mpu_dev= omap_device_get_by_hwmod_name("mpu");
  1792.   opp_enable(mpu_dev,
  1793.        AM33XX_ES2_0_OPPTURBO_FREQ);
  1794.   opp_enable(mpu_dev,
  1795.        AM33XX_ES2_0_OPPNITRO_FREQ);
  1796. }
  1797. /*SmartReflex also requires board information. */
  1798. am33xx_sr_init();
  1799. return;
  1800. out:
  1801. /*
  1802.   * If the EEPROM hasn't been programed or an incorrect header
  1803.   * or board name are read then the hardware details are unknown.
  1804.   * Notify the user and call machine_halt to stop the boot process.
  1805.   */
  1806. pr_err("The error message above indicates that there is an issuewith\n"
  1807.      "the EEPROM or the EEPROM contents.  Afterverifying the EEPROM\n"
  1808.      "contents, if any, refer to the %s function inthe\n"
  1809.      "%s file to modify the board\n"
  1810.      "initialization code to match the hardwareconfiguration\n",
  1811.      __func__ , __FILE__);
  1812. machine_halt();
  1813. }
  1814. static structat24_platform_data am335x_daughter_board_eeprom_info = {
  1815. .byte_len       = (256*1024) / 8,
  1816. .page_size      = 64,
  1817. .flags          =AT24_FLAG_ADDR16,
  1818. .setup          =am335x_setup_daughter_board,
  1819. .context        = (void *)NULL,
  1820. };
  1821. static structat24_platform_data am335x_baseboard_eeprom_info = {
  1822. .byte_len       = (256*1024) / 8,
  1823. .page_size      = 64,
  1824. .flags          =AT24_FLAG_ADDR16,
  1825. .setup          =am335x_evm_setup,
  1826. .context        = (void *)NULL,
  1827. };
  1828. static structregulator_init_data am335x_dummy = {
  1829. .constraints.always_on = true,
  1830. };
  1831. static structregulator_consumer_supply am335x_vdd1_supply[] = {
  1832. REGULATOR_SUPPLY("vdd_mpu", NULL),
  1833. };
  1834. static structregulator_init_data am335x_vdd1 = {
  1835. .constraints = {
  1836.   .min_uV   = 600000,
  1837.   .max_uV   = 1500000,
  1838.   .valid_modes_mask = REGULATOR_MODE_NORMAL,
  1839.   .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE,
  1840.   .always_on  = 1,
  1841. },
  1842. .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
  1843. .consumer_supplies = am335x_vdd1_supply,
  1844. .ignore_check_consumers = 1,
  1845. };
  1846. static structregulator_consumer_supply am335x_vdd2_supply[] = {
  1847. REGULATOR_SUPPLY("vdd_core", NULL),
  1848. };
  1849. static structregulator_init_data am335x_vdd2 = {
  1850. .constraints = {
  1851.   .min_uV   = 600000,
  1852.   .max_uV   = 1500000,
  1853.   .valid_modes_mask = REGULATOR_MODE_NORMAL,
  1854.   .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE,
  1855.   .always_on  = 1,
  1856. },
  1857. .num_consumer_supplies = ARRAY_SIZE(am335x_vdd2_supply),
  1858. .consumer_supplies = am335x_vdd2_supply,
  1859. .ignore_check_consumers = 1,
  1860. };
  1861. staticstruct tps65910_boardam335x_tps65910_info= {
  1862. .tps65910_pmic_init_data[TPS65910_REG_VRTC] =&am335x_dummy,
  1863. .tps65910_pmic_init_data[TPS65910_REG_VIO] =&am335x_dummy,
  1864. .tps65910_pmic_init_data[TPS65910_REG_VDD1] =&am335x_vdd1,
  1865. .tps65910_pmic_init_data[TPS65910_REG_VDD2] =&am335x_vdd2,
  1866. .tps65910_pmic_init_data[TPS65910_REG_VDD3] =&am335x_dummy,
  1867. .tps65910_pmic_init_data[TPS65910_REG_VDIG1] =&am335x_dummy,
  1868. .tps65910_pmic_init_data[TPS65910_REG_VDIG2] =&am335x_dummy,
  1869. .tps65910_pmic_init_data[TPS65910_REG_VPLL] =&am335x_dummy,
  1870. .tps65910_pmic_init_data[TPS65910_REG_VDAC] =&am335x_dummy,
  1871. .tps65910_pmic_init_data[TPS65910_REG_VAUX1] =&am335x_dummy,
  1872. .tps65910_pmic_init_data[TPS65910_REG_VAUX2] =&am335x_dummy,
  1873. .tps65910_pmic_init_data[TPS65910_REG_VAUX33] =&am335x_dummy,
  1874. .tps65910_pmic_init_data[TPS65910_REG_VMMC] =&am335x_dummy,
  1875. };
  1876. /*
  1877. * Daughter board Detection.
  1878. * Every board has a ID memory (EEPROM) on board. We probe these devices at
  1879. * machine init, starting from daughter board and ending with baseboard.
  1880. * Assumptions :
  1881. * 1. probe for i2c devicesare called in the order they are included in
  1882. *    the below struct. Daughter boards eeprom are probed 1st.Baseboard
  1883. *    eeprom probe is called last.
  1884. */
  1885. static struct i2c_board_info__initdata am335x_i2c0_boardinfo[]= {
  1886. #if 1
  1887. {
  1888. /* Daughter Board EEPROM */
  1889.   I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
  1890.   .platform_data  = &am335x_daughter_board_eeprom_info,
  1891. },
  1892. {
  1893.   /* Baseboard board EEPROM */
  1894.   I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
  1895.   .platform_data  = &am335x_baseboard_eeprom_info,
  1896. },
  1897. #endif
  1898. /*{
  1899.   I2C_BOARD_INFO("cpld_reg",0x35),
  1900. },*/

  1901. {
  1902.   I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
  1903.   .platform_data  = &am335x_tps65910_info,
  1904. },

  1905. {
  1906.   I2C_BOARD_INFO("sgtl5000",0x0A),
  1907.   
  1908. },


  1909. };
  1910. static structomap_musb_board_data musb_board_data = {
  1911. .interface_type = MUSB_INTERFACE_ULPI,
  1912. /*
  1913.   * mode[0:3] = USB0PORT's mode
  1914.   * mode[4:7] = USB1PORT's mode
  1915.   * AM335X beta EVM has USB0 inOTG mode and USB1 in hostmode.
  1916.   */
  1917. .mode           =(MUSB_HOST << 4) | MUSB_OTG,
  1918. .power  = 500,
  1919. .instances = 1,
  1920. };
  1921. static intcpld_reg_probe(struct i2c_client*client,
  1922.      const struct i2c_device_id *id)
  1923. {
  1924. cpld_client = client;
  1925. return 0;
  1926. }
  1927. static int__devexit cpld_reg_remove(struct i2c_client*client)
  1928. {
  1929. cpld_client = NULL;
  1930. return 0;
  1931. }
  1932. static conststruct i2c_device_idcpld_reg_id[] = {
  1933. { "cpld_reg", 0 },
  1934. { }
  1935. };
  1936. static structi2c_driver cpld_reg_driver = {
  1937. .driver = {
  1938.   .name = "cpld_reg",
  1939. },
  1940. .probe  = cpld_reg_probe,
  1941. .remove  = cpld_reg_remove,
  1942. .id_table = cpld_reg_id,
  1943. };
  1944. static voidevm_init_cpld(void)
  1945. {
  1946. i2c_add_driver(&cpld_reg_driver);
  1947. }
  1948. static void__init am335x_evm_i2c_init(void)
  1949. {
  1950. /* Initially assume General Purpose EVM Config */
  1951. am335x_evm_id = GEN_PURP_EVM;
  1952. setup_pin_mux(i2c0_pin_mux);
  1953. //evm_init_cpld();
  1954. omap_register_i2c_bus(1, 100, am335x_i2c0_boardinfo,
  1955.     ARRAY_SIZE(am335x_i2c0_boardinfo));
  1956. }
  1957. void __iomem*am33xx_emif_base;
  1958. void __iomem* __init am33xx_get_mem_ctlr(void)
  1959. {
  1960. am33xx_emif_base= ioremap(AM33XX_EMIF0_BASE, SZ_32K);
  1961. if(!am33xx_emif_base)
  1962.   pr_warning("%s: Unable to map DDR2controller", __func__);
  1963. returnam33xx_emif_base;
  1964. }
  1965. void __iomem*am33xx_get_ram_base(void)
  1966. {
  1967. return am33xx_emif_base;
  1968. }
  1969. void __iomem*am33xx_gpio0_base;
  1970. void __iomem*am33xx_get_gpio0_base(void)
  1971. {
  1972. am33xx_gpio0_base = ioremap(AM33XX_GPIO0_BASE, SZ_4K);
  1973. returnam33xx_gpio0_base;
  1974. }
  1975. static structresource am33xx_cpuidle_resources[] = {
  1976. {
  1977.   .start  = AM33XX_EMIF0_BASE,
  1978.   .end  = AM33XX_EMIF0_BASE + SZ_32K - 1,
  1979.   .flags  = IORESOURCE_MEM,
  1980. },
  1981. };
  1982. /* AM33XXdevices support DDR2 power down */
  1983. static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
  1984. .ddr2_pdown = 1,
  1985. };
  1986. static structplatform_device am33xx_cpuidle_device = {
  1987. .name   = "cpuidle-am33xx",
  1988. .num_resources  = ARRAY_SIZE(am33xx_cpuidle_resources),
  1989. .resource  = am33xx_cpuidle_resources,
  1990. .dev = {
  1991.   .platform_data = &am33xx_cpuidle_pdata,
  1992. },
  1993. };
  1994. static void__init am33xx_cpuidle_init(void)
  1995. {
  1996. int ret;
  1997. am33xx_cpuidle_pdata.emif_base= am33xx_get_mem_ctlr();
  1998. ret =platform_device_register(&am33xx_cpuidle_device);
  1999. if(ret)
  2000.   pr_warning("AM33XX cpuidle registration failed\n");
  2001. }
  2002. static void__init am335x_evm_init(void)
  2003. {
  2004. am33xx_cpuidle_init();
  2005. am33xx_mux_init(board_mux);
  2006. omap_serial_init();
  2007. am335x_evm_i2c_init();
  2008. omap_sdrc_init(NULL, NULL);
  2009. usb_musb_init(&musb_board_data);
  2010. omap_board_config = am335x_evm_config;
  2011. omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
  2012. /* Create an alias for icss clock */
  2013. if (clk_add_alias("pruss", NULL, "pruss_uart_gclk",NULL))
  2014.   pr_warn("failed to create an alias: icss_uart_gclk -->pruss\n");
  2015. /* Create an alias for gfx/sgx clock */
  2016. if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
  2017.   pr_warn("failed to create an alias: gfx_fclk -->sgx_ck\n");
  2018. }
  2019. static void__init am335x_evm_map_io(void)
  2020. {
  2021. omap2_set_globals_am33xx();
  2022. omapam33xx_map_common_io();
  2023. }
  2024. MACHINE_START(AM335XEVM,"am335xevm")
  2025. /* Maintainer: Texas Instruments */
  2026. .atag_offset = 0x100,
  2027. .map_io  = am335x_evm_map_io,
  2028. .init_early = am33xx_init_early,
  2029. .init_irq = ti81xx_init_irq,
  2030. .handle_irq     = omap3_intc_handle_irq,
  2031. .timer  = &omap3_am33xx_timer,
  2032. .init_machine = am335x_evm_init,
  2033. MACHINE_END
  2034. MACHINE_START(AM335XIAEVM,"am335xiaevm")
  2035. /* Maintainer: Texas Instruments */
  2036. .atag_offset = 0x100,
  2037. .map_io  = am335x_evm_map_io,
  2038. .init_irq = ti81xx_init_irq,
  2039. .init_early = am33xx_init_early,
  2040. .timer  = &omap3_am33xx_timer,
  2041. .init_machine = am335x_evm_init,
  2042. MACHINE_END
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