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错误代码是
我是照着韦山东那本书上编译的。。。没移植的时候编译能编译通过。。移植我是照着书上改的,修改的修改了100ask24x0.c和speed.c 自己看了很久都不知道为什么。。。。谢谢大家了
编译器我用的是3.4.5的。。。。。。。。。。。。
speed.c代码如下
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
#define MPLL 0
#define UPLL 1
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
DECLARE_GLOBAL_DATA_PTR;
static ulong get_PLLCLK(int pllreg)
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
ulong r, m, p, s;
if (pllreg == MPLL)
r = clk_power->MPLLCON;
else if (pllreg == UPLL)
r = clk_power->UPLLCON;
else
hang();
m = ((r & 0xFF000) >> 12) + 8;
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
if(gd->bd->bi_arch_number==MACH_TYPE_SMDK2410)
return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
else
return((CONFIG_SYS_CLK_FREQ*m*2)/(p<<s));
}
/* return FCLK frequency */
#define S3C2440_CLKDIVN_PDIVN (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
#define S3C2440_CLKDIVN_UCLK (1<<3)
#define S3C2440_CAMDIVN_CAMCLK_MASK (0XF<<0)
#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
#define S3C2440_CAMDIVN_CAMCLK_DVSEN (1<<12)
ulong get_FCLK(void)
{
return(get_PLLCLK(MPLL));
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
unsigned long clkdiv;
unsigned long camdiv;
int hdiv=1;
if(gd->bd->bi_arch_number==MACH_TYPE_SMDK2410)
return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
else
{
clkdiv=clk_power->CLKDIVN;
camdiv=clk_power->CAMDIVN;
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
{
case S3C2440_CLKDIVN_HDIVN_1:
hdiv=1;
break;
case S3C2440_CLKDIVN_HDIVN_2:
hdiv=2;
break;
case S3C2440_CLKDIVN_HDIVN_4_8:
hdiv=(camdiv&S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
hdiv=(camdiv&S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
return get_FCLK()/hdiv;
}
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
unsigned long clkdiv;
unsigned long camdiv;
int hdiv=1;
if(gd->bd->bi_arch_number==MACH_TYPE_SMDK2410)
return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
else
{
clkdiv=clk_power->CLKDIVN;
camdiv=clk_power->CAMDIVN;
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
{
case S3C2440_CLKDIVN_HDIVN_1:
hdiv=1;
break;
case S3C2440_CLKDIVN_HDIVN_2:
hdiv=2;
break;
case S3C2440_CLKDIVN_HDIVN_4_8:
hdiv=(camdiv&S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
hdiv=(camdiv&S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
return get_FCLK()/hdiv/((clkdiv&S3C2440_CLKDIVN_PDIVN)?2:1);
}
}
#endif
100ask24x0.c大妈如下
#include <common.h>
#include <s3c2410.h>
DECLARE_GLOBAL_DATA_PTR;
#define S3C2440_MPLL_400MHZ ((0X5C<<12)|(0X01<<4)|(0X01))
#define S3C2440_UPLL_48MHZ ((0X38<<12)|(0X02<<4)|(0X02))
#define S3C2440_CLKDIV 0X05
#define S3C2410_MPLL_200MHZ ((0X5C<<12)|(0X04<<4)|(0X00))
#define S3C2410_UPLL_48MHZ ((0X28<<12)|(0X01<<4)|(0X02))
#define S3C2410_CLKDIV 0X03
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
S3C24X0_CLOCK_POWER * const clk_power=S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x00044555;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFF95FFBA;
gpio->GPGUP = 0x0000FFFF;
gpio->GPHCON = 0x002AFAAA;
gpio->GPHUP = 0x000007FF;
if((gpio->GSTATUS1==0X32410000)||(gpio->GSTATUS1==0X32410002))
{
clk_power->CLKDIVN=S3C2410_CLKDIV;
__asm__("mrc p15,0,r1,c1,c0,0\n"
"orr r1,r1,#0xc0000000\n"
"mcr p15,0,r1,c1,c0,0\n"
:::"r1"
);
clk_power->LOCKTIME=0xFFFFFF;
clk_power->MPLLCON=S3C2410_MPLL_200MHZ;
delay(4000);
clk_power->UPLLCON=S3C2410_UPLL_48MHZ;
delay(8000);
gd->bd->bi_arch_number=MACH_TYPE_SMDK2410;
}
else
{
clk_power->CLKDIVN=S3C2440_CLKDIV;
__asm__("mrc p15,0,r1,c1,c0,0\n"
"orr r1,r1,#0xc0000000\n"
"mcr p15,0,r1,c1,c0,0\n"
:::"r1"
);
clk_power->LOCKTIME=0xFFFFFF;
clk_power->MPLLCON=S3C2440_MPLL_400MHZ;
delay(4000);
clk_power->UPLLCON=S3C2440_UPLL_48MHZ;
delay(8000);
gd->bd->bi_arch_number=MACH_TYPE_S3C2440;
}
gd->bd->bi_boot_params=0x30000100;
icache_enable();
dcache_enable();
return 0;
} |
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